SystemC Public Class in Austin, TX
Modeling & Verification with SystemC Workshop
This four-day event includes both a four-day workshop and a one day seminar. The four-day workshop introduces the student to modeling and verification with C/C++ and the SystemC C++ class library including the SystemC Verification library (2.0-SCV). It is intended for engineers who are new to SystemC or those who may be self-taught, with an interest in learning SystemC with a modeling and verification focus. SystemC Version 2.0 and SystemC Verification Library concepts are taught.
SystemC Functional level and transaction Level (TLM) modeling is covered. Communication refinement methodology and techniques are covered in depth. SystemC Verification concepts are taught. The student will learn how to write, compile, execute and debug system and hardware descriptions with SystemC.
This course mixes lecture with exercises for all major topics.
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Prerequisites
- Familiarity with Verilog, VHDL or C
Related Courses
- C++ for the HDL Engineer or C Programmer
A 2-day intro to C++ from a hardware or system modeling perspective
Course Outline
- Introduction
- SystemC modeling
- Basic modeling structure
- Getting started - running & debugging
- C++
- Streams, pointers and references, data abstraction
- Data hiding, initialization & cleanup
- Inheritance, overriding, overloading, const, templates, polymorphism
- Libraries (STL, BOOST)
- Modules
- Ports, Interfaces, & Channels
- Module constructor
- Events
- Processes in general
- Thread processes
- Method processes
- Module instantiation (in modules)
- sc_main
- Channels
- Time & clocks
- Module instantiation (in sc_main)
- Simulation functions
- SystemC data types
- Primitive channels
- User defined channels
- Communication refinement
- Channel refinement & adapters
- SystemC Verification
- Data Introspection
- Randomization
- Constraints
- Customizing Data Generation
- Sparse Arrays
Hands-On Labs
A large portion of class time will be spent applying principles learned in lecture to hands-on labs.
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