This four-day workshop introduces the student to modeling and verification with C/C++ and the SystemC C++ class library. It is intended for engineers who are new to SystemC or those who may be self-taught, with an interest in learning SystemC with a modeling focus.

SystemC Functional level and transaction Level (TLM) modeling is covered. Communication refinement methodology and techniques are covered in depth. The student will learn how to write, compile, execute and debug system and hardware descriptions with SystemC

This course is mixed lecture and exercises, with an exercise for nearly every topic.

Prerequisites

• Strong familiarity with Verilog, VHDL or C (at least one)

Related Courses

• C++ for the HDL Engineer or C Programmer
  A 2-day intro to C++ from a hardware or system modeling perspective

Course Outline

• Introduction
• SystemC modeling
• Basic modeling structure
• Getting started - running & debugging
• C++
  - Streams, pointers and references,
  data abstraction
  - Data hiding, initialization & cleanup
  - Inheritance, overriding, overloading,
  const, templates, polymorphism
  - Libraries (STL, BOOST)
• Modules
  - Ports, Interfaces, & Channels
  - Module constructor
  - Events
  - Processes in general
  - Thread processes
  - Method processes
  - Module instantiation (in modules)
• sc_main
  - Channels
  - Time & clocks
  - Module instantiation (in sc_main)
  - Simulation functions
• SystemC data types
• Primitive channels
• User defined channels
• Communication refinement
  - Channel refinement & adapter