This 2 day class is intended for the Verilog/VHDL engineer or C programmer who will be using C++ for modeling hardware or systems using C++, or C++ based languages such as SystemC.

The course introduces the student, in depth, to C++ syntax and concepts from a modeling, perspective. It is intended primarily for modeling and is not intended as a general C++ course.

This course is mixed lecture and exercises, with an exercise for nearly every topic.

Prerequisites

• Familiarity with Verilog, VHDL or C

Related Courses

• Modeling with SystemC
  Follow on class to this one

Course Outline

• Object Orientation
• Getting Started
• Program Structure
• Basic Language Elements
• More Data Types
• Streams & I/O
• Pointers & References
• Data Abstraction
• Data Hiding
• Initialization & Cleanup
• Overloading
• Constants
• Inheritance
• Templates
• Using the Standard Template Library (STL)