John Cooley, the well known "Industry Gadfly", EE Times Columnist and general
EDA industry pundit, has proposed a challenge to Brett Cline, SystemC evangelist
and Marketing wizard for Forte Design Systems. John is well known for his
attempts to make the EDA vendors come clean. Brett is well known for pushing
SystemC, which his company, Forte Design Systems, uses as input to their
algorithmic synthesis tool.

This survey is not all fun and games. It does contribute to the general view of
acceptance of all tools that it considers, which in turn affects the R&D budgets of
EDA companies and the funding decisions of Venture Capitalists. In general, it
affects the amount of  money invested in the tools that you are using or will be
using.

Please take a few minutes to answer the survey below. John & Brett will thank you.

To see the original challenge click HERE.

Do you use SystemC at your company? If yes, you can help Brett out by sending
John Cooley E-mail responding to his survey (see below). If you wish, you can
request anonymity. John is very good about this. Simply fill in the form below,
and we'll send you an e-mail with the survey ready to forward to John. His e-mail
address will be in the e-mail your receive.

IMPORTANT: Please fill out as much of the survey as you can. Also, the
survey must come from a company email account, as John tends to discard
e-mail from google.com, hotmail.com, netscape.com, and other public
addresses as potential SPAM or EDA vendors in disguise. When you fill out the
form below, we will mail back a formatted message with instructions for you to
copy, paste & send to John. We'll even include his e-mail address.

Your full name:

Your e-mail address:

Your company name:

1. If you need to be anonymous, say "Make Me Anon" here.
   
   Make Me Anonymous
   
   
2. Whose Verilog or VHDL simulator(s) do you currently use?
   Does your project do mixed Verilog/VHDL simulations? Yes No
   If yes, why?
   
   
3. Do you see your project using SystemC within the next 6 months? Yes No
   How are you using SystemC? High level modeling Verification Design
   (I'm talking about serious usage; not experimental use. If you're just playing with
   SystemC, please say "No" to these questions.)
   Whose SystemC tools are you using?
   
   
4. Do you see your project using System Verilog in the next 6 months? Yes No
   What are you using System Verilog for?
   What do you plan to use? 3.0 Designer Verification extensions Both
   (I'm talking about serious usage; not experimental use. If you're just playing
   with System Verilog, please say "No" to these questions.)
   Whose System Verilog tools are you using?
   
   
5. What do you think about Verisity Specman "e" vs. Synopsys Vera?
   
   Does your project use either of these? Specman Vera
   Who's ahead? Specman Vera
   How about alternatives like JEDA or SystemC SCV?
   Which of them are you using, if any?
   
   Where do you think specialty functional verification languages like Specman "e"
   and Vera be in 5 years? Dead An ever growing part of chip verification
   
   
6. What do you think of assertion languages and assertion libraries such as Sugar
   PSL, OVL, OVA, SVA, 0-In CheckerWare?
   Which do you use? Sugar PSL OVL OVA SVA 0-In CheckerWare
   Are they useful or busy work?
   
   
7. What linter/debug/coverage tools do you use?
   What do you think of Verisity SureCov and TransEDA and Summit HDLScore
   vs. the built-in coverage in Synopsys VCS, Cadence NC, Mentor ModelSim,
   and Aldec?
   
   What about Synopsys Leda, Cadence HAL or Mentor DesignAnalyst or
   Atrenta SpyGlass?
   Novas DeBussy & nSchema & Verdi, and Veritools Undertow?
   How about design entry tools like Summit Visual Elite or Mentor HDL Designer
   (Renoir)?
   
   
8. What tool do you use for equivalence checking? Cadence Verplex or Synopsys
   Formality or Mentor FormalPro or Prover eCheck?
   Who's ahead? Who's behind?
   
   
9. What do you think about "bug hunters" like 0-in, Jasper, @HDL, Real Intent,
   Averant, or Synopsys Magellan or Atrenta PeriScope?
   If your company uses such tools, which ones?
   Are they? Useful Waste of time
   
   
10. Does your company use HW emulators/accelerators like Cadence Palladium,
    Mentor IKOS/VStation/Celaro, Verisity Axis, Tharas, Pittsburgh Simulations,
    EVE ZeBu, or Aptix? Yes No
    What do you think about them?
    What type of set-up time do you see with them?
    
    
11. Do you use HW/SW co-simulation like CoWare ConvergenSC or Mentor
    Seamless or Aldec Riviera-IPT? Yes No
    Which?
    What do you think of them?
    
    
12. Does your company use verification IP? Yes No
    Which protocol(s)? USB, PCI, FireWire, Ethernet, AMBA, 1394
    Other IP:
    How is the IP used? Reference checking Bus-functional modeling (BFM)
    Measure coverage of the standard
    Whose IP do you use? Verisity Synopsys DesignWare Cadence Mentor
    CoWare Summit Others?
    
13. Other comments?